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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, 2001 zarlink semiconductor inc. all rights reserved. features ? loop start trunk interface ?600 ? ? 2-4 wire conversion ? line state detection outputs: ? forward loop ? reverse loop ? ringing voltage ? switch hook ? one relay driver ? on-hook reception ? small footprint area ? meets fcc part 68 leakage current requirements applications interface to central office for: ?pabx ? key telephone systems ? channel bank ?voice mail ? terminal equipment ? digital loop carrier ? optical multiplexer description the zarlink MH88634CV-K ce ntral office interface circuit trunk provides a complete analog and signalling link between audio switching equipment and a telephone line. the device is fabricated as a thick film hybrid incorporating various techno logies for optimum circuit design and very high reliability. the component design has been changed to improve the general performance of the part. it is also now capable of operating at a 24v battery and on hook reception. the main difference between the mh88634bv-2 and MH88634CV-K is that shk is active high on the cv-k. september 2003 ordering information MH88634CV-K 21 pin sil package 0 c to 70 c MH88634CV-K central office interface circuit data sheet figure 1 - functional block diagram status detection receive gain transmit gain 2 - 4 wire hybrid dummy ringer line termination loop relay driver impedance matching network balance xla xlb xlc xld lrc lrd vrly ring tip rv vcc rx tx vee agnd fl rl shk
MH88634CV-K data sheet 2 zarlink semiconductor inc. figure 2 - pin connections pin description pin # name description 1tip tip lead. connects to the "tip" lead of a telephone line. 2ring ring lead. connects to the "ring" lead of a telephone line. 3xla loop relay contact a. connects to xlb through the loop relay (k1) contacts when the relay is activated. 4xld loop relay contact d. connects to xlc through the loop relay (k1) contacts, when the relay is activated. 5xlb loop relay contact b. connects to xla through the loop relay (k1) contacts, when the relay is activated. 6xlc loop relay contact c. connects to xld through the loop relay (k1) contacts, when the relay is activated. 7-9 ic internal connection. no connection should be made to this pin. 10 shk switch hook (output). a logic 0 indicates the presence of forward or reverse battery voltage when lrc is logic 0 and the presence of forward or reverse loop current when lrc is logic 1. 11 rx receive (input). 4-wire ground (agnd) referenced analog input. 12 vee negative supply voltage. -5v dc 13 tx transmit (output). 4-wire ground (agnd) referenced analog output. 14 rv ringing voltage detect (output). a logic low indicates that ringing voltage is across the tip and ring leads. 15 fl forward loop detect (output). in the on-hook state, a logic 0 output indicates that forward loop battery is present. in the off-hook state, a logic 0 indicates that forward loop current is present. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 tip ring xla xlb xlc ic ic ic rx vee tx rv fl rl vcc agnd lrc vrly lrd 21 xld shk
MH88634CV-K data sheet 3 zarlink semiconductor inc. functional description the MH88634CV-K is a central office interface circuit (coic ). it is used to correctly terminate a central office 2- wire telephone line. the device provides a signalling link and a 2-4 wire line interface between the telephone line and subscriber equipme nt. the subscriber equipment can include private branch exchanges (pbxs), key telephone systems, terminal equipment, digital loop carriers and wireless local loops. all descriptions assume that the device is connect ed as in the application circuit shown in figure 3. isolation barrier the MH88634CV-K provides an isolation barrier which is designed to meet fcc part 68 (november 1987) leakage current requirements. external protection circuit an external protection circuit device assists in preven ting damage to the device and the subscriber?s equipment, due to over-voltage conditions. the type of protection re quired is dependant upon the application and regulatory standards. further details should be obtained from the s pecific country?s regulatory body. typically you will need lightening protection supplied by resettable fuses or ptc tm and mains crossover protection via a foldover diode. suitable markets the MH88634CV-K has fixed 600 ? line and network balance impedance for use in north america and asia. line termination when lrc is at a logic 1, lrd will sink current which energizes the loop relay (k1), connecting xla to xlb and xlc to xld. this places a line termination across tip and ring. the device can be considered to be in an off-hook state and dc loop current will flow. the line termination consists of a dc resistance and an ac impedance. when lrc is at a logic 0, the line termination is removed from across tip and ring. an internal dummy ringer is permanently connected across tip and ring which is a series ac load of (17k ? +330nf). this represents a mechanical telephone ringer and allows ringing voltages to be sensed. this load can be considered negligible when the line has been terminated. depending on the network protocol being used the line termination can terminate an incoming call, seize the line for an outgoing call, or if applied and disconnected at the correct rate can be used to generate dial pulse signals. 16 rl reverse loop detect (output). in the on-hook state, a logic 0 output indicates that reverse loop battery is present. in the off-hook state, a logic 0 output indicates that reverse loop current is present. 17 vcc positive supply voltage. +5v dc 18 agnd analog ground. 4-wire ground (agnd). normall y connected to system ground. 19 lrc loop relay control (input). a logic 1 activates the loop relay driver output (lrd ). 20 vrly relay positive supply voltage. typically +5v. connects to the relay supply voltage. 21 lrd loop relay drive (output). connects to the loop relay coil. when lrc is at a logic 1 an open collector output at lrd sinks current and energizes the relay. pin description (continued) pin # name description
MH88634CV-K data sheet 4 zarlink semiconductor inc. the dc line termination circuitry provides the line with an active dc load termination which is equivalent to a dc resistance of 280 ? at 20ma. ringing equivalent number the ringing equivalent number (ren) is application specif ic. see the governing regulatory body specification for details. input impedance the input impedance (zin) is the ac impedance that the MH88634CV-K places across tip and ring to terminate the telephone line. this is fixed at 600 ? . network balance impedance the MH88634CV-K network balance impedance is fixed at 600 ? . 2-4 wire conversion the device converts the balanced 2-wire input, presented by the line at tip and ring, to a ground referenced signal at tx. this circuit operates with or without loop current; si gnal reception with no loop current is required for on-hook reception enabling the detection of caller line identification (cli) signals. conversely, the device converts the ground referenced signa l input at rx, to a balanced 2-wire signal across tip and ring. the 4-wire side (tx and rx) can be interfaced to a filter/c odec, such as the zarlink mt896x, for use in digital voice switched systems. during full duplex transmission, the signal at tip and ring consists of both the signal from the device to the line and the signal from the line to the device. the signal input at rx, being sent to the line, must not appear at the output tx. in order to prevent this, the device has an internal cancellation circuit. the measure of attenuation is transhybrid loss (thl). transmit and receive gain the transmit gain of the device is t he gain from the balanced signal across tip and ring to the ground referenced signal at tx. it is set at 0db. the receive gain of the device is the gain from the ground referenced signal at rx to the balanced signal across tip and ring. it is set at -2db. supervision features line status detection outputs the MH88634CV-K supervi sory circuitry provides the signalling status outputs whic h are monitored by the system controller. the supervisory circuitry is capable of detecting: ringing voltage; forward and reverse loop battery; forward and reverse loop current; and switch hook. ringing voltage detect output (rv) the rv output provides a logic 0 when ringing voltage is de tected across tip and ring. this detector includes a filter which ensures that the output toggles at the ringing cadence and not at the ringing frequency. typically this
MH88634CV-K data sheet 5 zarlink semiconductor inc. output switches to a logic 0 after 50ms of applied ringing voltage and remains at a logic 0 for 50ms after ringing voltage is removed. rv shall not toggle during ringing. forward loop and reverse loop detect outputs (fl & rl ) the fl output provides a logic 0 when either forward loop battery or forward loop current is detected, that is the ring pin voltage is more negative than the tip pin voltage. the rl output provides a logic 0 when either reverse loop batt ery or reverse loop current is detected, that is the tip pin voltage is more negative than the ring pin voltage. switch hook (shk) the shk output is active if either forward loop or reverse loop current is detected, or if forward or reverse battery voltage is detected. control input the MH88634CV-K accepts a control sig nal from the system controller at th e loop relay control input (lrc). this energizes the relay drive output loop relay drive (lrd ). the output is active low and has an internal clamp diode to vrly. the intended use of this relay driver is to add and remo ve the line termination from across tip and ring, as shown in figure 3. if this control input and the supervisory features are used as indicated in figure 3, loop-start signalling can be implemented. mechanical data see figure 9 for details of the mechanical specification.
MH88634CV-K data sheet 6 zarlink semiconductor inc. figure 3 - typical ls application circuit *exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c with nominal 5v supplies and are for design aid only. absolute maximum ratings* parameters sym min max units comments 1 dc supply voltages v cc v ee -0.3 0.3 7 -7 v v 2 dc ring relay voltage v rly -0.3 18 v 3 storage temperature t s -55 +125 c 4 ring trip current i trip 180 marms 250ms 10% duty cycl e or 500ms single shot recommended operating conditions parameters sym min typ ? max units 1 dc supply voltages v cc v ee 4.75 -4.75 5.0 -5.0 5.25 -5.25 v v 2 dc ring relay voltage v rly 5.0 15 v 3 operating temperature t op 02570c mh88634 analog out analog in ringing detect forward loop reverse loop switch hook -5v +5v k1 protection circuit tip ring loop relay control tip ring lrd vrly lrc xla xlb xlc xld vcc agnd vee shk rl fl rv rx tx k1 notes: 1) k1 electro mechanical 2 form a k1 c1 c2 2) c1 and c2 are decoupling capacitors 5 3 15 16 6 10 4 18 12 14 19 21 2 20 11 13 17 1 +5v
MH88634CV-K data sheet 7 zarlink semiconductor inc. s ? electrical characteristics are over recommend ed operating conditions unless otherwise stated. ? typical figures are at 25 c with nominal 5v supplies and are for design aid only. ? electrical characteristics are over recommend ed operating conditions unless otherwise stated. ? typical figures are at 25 c with nominal 5v supplies and are for design aid only. note 1: maximum figure of 282 ? at 0 c dc electrical characteristics ? characteristics sym min typ ? max units test conditions 1 supply current i cc i ee 5 2.5 13 13 ma ma 2 power consumption pc 37.5 137 mw v bat not connected 3fl rl shk rv low level output voltage high level output voltage v ol v oh 2.4 0.5 v v i ol = 4ma i oh = 0.4ma 4lrd sink current, relay to v cc clamp diode current i ol i cd 100 150 ma ma v ol = 0.5v not continuous, lrc=5v 5 lrc low level input voltage high level input voltage v il v ih 3.20 0.8 v v 6 lrc high level input current low level input current i ih i il 40 40 a a v ih = 5.0v loop electrical characteristics ? characteristics sym min typ ? max units test conditions 1 ringing voltage vr 40 90 150 v rms 17 to 68hz 2 operating loop current 16 85 ma 3 off-hook dc resistance 270 280 ? @ 20ma note 1 4 leakage current (tip-ring to agnd) 7 marms @ 1000vac 5shk & fl threshold tip-ring (on-hook) tip-ring current (off-hook) 12 10.5 21 15 vdc ma lrc = 0v lrc = 5v 6 shk & rl threshold tip-ring (on-hook) tip-ring current (off-hook) 12 10.5 21 -15 vdc ma lrc = 0v lrc = 5v
MH88634CV-K data sheet 8 zarlink semiconductor inc. ? electrical characteristics are over recommend ed operating conditions unless otherwise stated. ? typical figures are at 25 c with nominal 5v supplies and are for design aid only. ac electrical characteristics ? characteristics symbol min typ ? max units test conditions 1 2-wire input impedance zin 600 ? -2 variant 2 return loss at 2-wire rl 20 29 db test circuit as fig 6 200-3400 hz 3 longitudinal to metallic balance 58 55 53 60 60 58 db db db test circuit as fig 7 200hz 1000hz 3400hz 4 transhybrid loss thl 20 27 db 200-3400hz 5 gain, 2 wire to tx relative gain -0.25 -0.3 0 0 0.25 0.3 db db test circuit as fig 4 1000hz 200-3400hz 6 gain, rx to 2 wire relative gain -2.25 -0.3 -2 0 -1.75 0.3 db db test circuit as fig 5 1000hz 200-3400hz 7 input impedance at rx 10 k ? 8 output impedance at tx 5 ? 9 signal overload level at 2-wire at tx 4.0 1.7 dbm dbm % thd < 5% @ 20ma 10 total harmonic distortion at 2-wire at tx thd 1.0 1.0 % % input 0.5v, 1khz @ rx input 0.5v, 1khz @ tip-ring 11 idle channel noise at 2-wire at tx nc 1 5 15 16.5 16.5 dbrnc dbrnc 12 power supply rejection ratio at 2-wire and tx v cc v ee psrr 25 25 48 47 db db ripple 0.1v, 1khz 13 on-hook gain, 2-wire to tx relative to off-hook gain -1 0 1 db input 1000hz @ 0.5v 14 met. to long. balance -2 variant -4 variant 60 40 55 40 62 48 62 48 test circuit as fig. 8 200-1000hz 1000-3400hz 200-1000hz 1000-3400hz 15 common mode rejection ratio cmrr 48 55 db test circuit as fig. 7 1000hz, fl = 0v, i loop = 25ma
MH88634CV-K data sheet 9 zarlink semiconductor inc. figure 4 - 2-4 wire gain test circuit figure 5 - 4-2 wire gain test circuit ~ 100uf ring tip xla xlb xlc xld vs = 0.5v 600 ? agnd vcc vee rx tx 100uf +5v -5v i = 25ma 10h 300 ? 10h 300 ? + + gain = 20 * log (vtx/vs) -v v tx v ~ vs = 0.5v z = 600 ? gain = 20 * log (vz/vs) 100uf -v ring tip xla xlb xlc xld agnd vcc vee rx tx 100uf +5v -5v i = 25ma 10h 300 ? 10h 300 ? + + vz
MH88634CV-K data sheet 10 zarlink semiconductor inc. figure 6 - return loss test circuit figure 7 - longitudinal to metallic balance and cmrr test circuit 600 ? 368 ? v1 return loss = 20 * log (v1\vs) ~ 100uf -v ring tip xla xlb xlc xld vs = 0.5v agnd vcc vee rx tx 100uf +5v -5v i = 25ma 10h 300 ? 10h 300 ? + + 368 ? 368 ? v1 long to met bal. = 20 * log (v1\vs) ~ 100uf -v ring tip xla xlb xlc xld vs = 0.5v agnd vcc vee rx tx 100uf +5v -5v i = 25ma 10h 300 ? 10h 300 ? + + 368 ? cmrr = 20 * log (vtx\vs) - ( 2-4w gain) vex v v tx
MH88634CV-K data sheet 11 zarlink semiconductor inc. figure 8 - metallic to longitudinal balance test circuit figure 9 - mechanical data 368 ? v1 met to long bal. = 20 * log (v1\vs) ~ 100uf -v ring tip xla xlb xlc xld vs = 0.5v agnd vcc vee rx tx 100uf +5v -5v i = 25ma 10h 300 ? 10h 300 ? + + 368 ? 510 ? 1 0.625 max (15.9 max) 0.020 + 0.005 (0.5 + 0.13) 0.100 + 0.010 (1.52+ 0.05) 0.06+ 0.02 0.180 + 0.020 (4.57 + 0.51) (2.54 + 0.25) * * 0.14 max (3.6 max) 0.010 + 0.002 (0.25 + 0.05) 0.13 max (3.3 max) notes: 1) not to scale 2) dimensions in inches. (dimensions in millimetres) * dimensions to centre of pin. 3) pin tolerances are non-accumulative. 4) recommended soldering conditions: wave soldering temperature 260c for 10 secs. 2.120 max (53.85 max)
MH88634CV-K data sheet 12 zarlink semiconductor inc. figure 10 - MH88634CV-Kt-2 mechanical information 1 2.12 max (53.85 max) 0.260 + 0.015 (6.60 + 0.38) 0.080 + 0.020 (2.03 + 0.51) 0.080 max (2.03 max) 0.170 max (4.32 max) 0.100 0.010 0.020 + 0.005 (0.51 + 0.13) (2.54 0.25) * (15.75 max) 0.62 max notes: 1) not to scale 2) dimensions in inches. (dimensions in millimetres) * dimensions to centre of pin. 3) pin tolerances are non-accumulative. 4) recommended soldering conditions: wave soldering - max temp at pins 260 for 10 secs. 0.250 0.020 (6.35 0.51)
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